Prior art logic analyzers provide merely for enabling the storage of input data states in response to a selected number of satisfactions of a single preselected qualifier state condition and for the storage of data states satisfying a second qualifier state condition. Display modes have comprised formatted listings or certain vector mappings based solely on the entire data state stored.
The present invention incorporates multiple triggering circuits of the type described in the referenced patent application entitled DIGITAL PATTERN TRIGGERING CIRCUIT. These triggering circuits provide output signals in response to an input data state satisfying one of the pre-selected qualifier state conditions. A counter and related sequencing logic is coupled to a first set of triggering circuits to determine when the storage of input data states should be enabled. A separate triggering circuit provides a signal to the sequencing logic for restarting the enabling sequence in response to the detection of a restart state condition. Storage of data states is further qualified by a second set of triggering circuits. The output of this set is logically OR'ED and supplied to the memory logic so that only data states meeting one of the pre-selected state conditions are stored. A second memory is loaded in parallel with the storage of a data state into the first memory. The data loaded into the second memory comprises the content of a binary counter. The binary counter can be coupled to either an internal clock so that the time relationship between stored states can be determined, or alternatively, to a count trigger circuit so that the counter can count occurrences of a predefined data state. The count triggering circuit allows for the determination of the number of occurrences of the input data states satisfying a count qualifier state condition intermediate to the storage of selected data states.
Input data states can be formatted by assigning certain contiguous sets of bits to letter labels. Each label is subsequently treated as an independently addressable field and an independent radix can be selected for each label. Subsequent operation and references to the input data are now made by referring to these labels. In the tabular display the label fields are concatenated in alphabetical order.
An alternate graphical display plots the binary magnitude of the stored bits corresponding to a selected label field as a function of the respective location in storage.